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There are a lot of PCB design fans who are very fond of designing PCB boards by themselves. Today, let's share the basic rules of PCB wire layout with you, details as follows:

Basic rules for PCB wire layout

1. Basic rules of components layout

⑴ According to the circuit module, we call it module for the relevant circuit that realizing the same function, and the components in the circuit module should adopt the principle of concentration, and the digital circuit and the simulated circuit should be separated;

⑵ Components or devices an not be assembled within 1.27mm around the non-mounting  holes like tooling holes and standard holes and no components within 3.5mm (for M2.5)  and 4mm (for M3) around the mounting holes such as screws holes;

⑶ Avoid via holes under the components such as the resistance, inductance (pressfit) andelectrolytic capacitor so as to avoid short-circuit between the via hole and the component after wave soldering;

⑷ The distance between the outer side of the component and the board edge is 5mm;

⑸ The distance between the outer side of the SMT component pad and the outer side ofthe neighbouring press-fit component should be greater than 2mm;

⑹ Metal shell components and metal parts (shield boxes, etc.) cannot contact with other components, and should not be close to the printed wires or pads, and the spacing should be greater than 2mm. The distance between the board edge and the out side of the tooling holes, fastener mounting holes, oval holes and other holes inside the board should be larger than 3mm;

⑺ The heating components cannot be close to the neighbouring conductor wire and the  thermo-sensitive components; the high-heat devices should be evenly distributed;

⑻ The power socket should be placed around the PCB and the GND terminal of the bus bar between the power socket and its connection should be arranged on the same side.Especial do not place the power socket and other soldering connectors between connectorwhich is prone to the soldering, designing and cable binding. The spacing between the power socket and the soldering connector should be considered if it's convenient for thepower socket to plug in and out;

⑼ Placement of other components;

All IC components should be aligned per side, and clear marking for polar components. The polar markings on the same PCB can not be more than 2 directions. When there are2 directions, these 2 directions should be mutually perpendicular;

⑽ The density off board layout should be proper. When the difference in density is too big, it should be filled with mesh copper foil. Width of the mesh should be larger than 8mil (or 0.2mm);

⑾ There should be no through holes on the SMT pads to avoid solder paste loss or poor soldering for components. Important signal lines are not allowed to pass through between the socket pins;

⑿ SMT pads should be aligned per side, component mark and the assembling direction should be the same;

⒀ Directions of polar markings on the same board should be consistent with each other.

2. Layout rules for component wires

⑴ It is prohibited for wire layout within ≤1mm from the PCB board edge and within 1mm around the mounting holes;

⑵ The power lines should be as wide as possible, not less than 18 mils; width of signal lines should not be less than 12 mils; the cpu lines should not be less than 10 mils (or 8 mils); the line spacing should be no less than 10 mils;

⑶ Normally via holes should not less than 30mil;

⑷ Dual press fit: pad 60mil, hole dia.: 40mil;1/4W resistance: 51*55mil (0805 surface SMT); press fit pad: 62 mil, hole dia.: 42 mil;

Non-polar capacitance: 51*55mil (0805 surface SMT); press fit pad: 50mil; hole dia.: 28mil; 50mil, hole dia.: 28mil;

⑸ Pls note that the power and ground wires should be radiative, and the signal wires cound not have loopback traces.

How to improve anti-interference ability and EMC when developing electronic productswith processors?

1、 Pay more attention to the anti-electromagnetic interference for the systems below:

⑴ Clock frequency of the microcontroller is particularly high, for a system with very fast bus trunk cycle.

⑵ The system contains high-power, high-current driving circuits, such as spark-generating relays, high-current switches, and so on.

⑶ For system contains weak simulation signal circuit and high precision A/D conversion circuit.

2、In order to increase the interference capability of anti-electromagnetic for the system, 

the following measures should be taken:

⑴ Use a low frequency microcontroller:

The use of a microcontroller with a low external clock frequency can effectively reduceThe noise and improve the anti-interference ability for the system. For square waves and sine waves of the same frequency, the high frequency in the square wave are much more than the sine waves. Although the high-frequency in square wave is smaller than the fundamental wave, but higher the frequency is, the easier to launch as the noise source, and the high-frequency noise generated by the microcontroller is about 3 times than the clock frequency.

⑵ Reduce distortion in signal transmission

Microcontrollers are mainly manufactured by using high speed CMOS technology. The static input current at the signal terminal is about 1mA, input capacitance is about 10PF, the input impedance is quite high. The output of the high-speed CMOS circuit has large carrying and loading capacity, that is, considerable output value, the output end can pass trough to the high end which has a high impedance via a very long leading wire. The reflection will be a serious problem which will causes signal distortion and increases system noise. When Tpd>Tr, it becomes a transmission line problem, and signal reflection, impedance matching issues must be taken into consideration.

The time of delay of the signal on PCB is related to the coated micro-strip impedance of the leading wires, which is related to the dielectric constant of the PCB materials. It can be roughly assumed that the transmission speed of the signal on the PCB wire leads is 1/3 or 1/2 of the speed of light. The Tr (standard delay time), one of the normal logical phone components in microcontroller system is about 3 to 18ns.

On a PCB, the signal can passe through 7W resistance and 25cm long wire lead, time ofdelay is approximately 4~20ns. That is to say, the shorter the wire lead is, the better thesignal is. The length should ot exceed 25cm. And the numbers of vias holes should be 

reduced as many as possible, no more than 2.

When the rising time of the signal is faster than the time of delay,  then it should be processed according to fast electronics. At this time, the impedance matching of the transmission line should be considered. For the signal transmission between the integrationon a PCB, Td>Trd should be avoided, the larger the system is, the slower the speed is.

Use the following conclusions to summarize a rule for PCB design:

The signal is transmitted on the PCB and the time of delay should not be greater than the nominal time of delay time of the devices used.

⑶ Reduce the interference between signal lines:

At point A, a signal with a rising time Tr is transmitted through the wire lead AB to B.The time of delay of the signal on AB line is Td. At point D, due to the forward transmission of the A signal, and the signal reflection after reaching point B and the timeof delay of AB, time TD can feel a pulse signal of width Tr. At point C, due to the transmission and reflection of the signal on AB, it can feel the time of delay which is 2 times wider than on AB, that is, a positive pulse signal of 2Td. This is the interference between the signals. The strength of the interfering signal is related to the di/at of signal C and the line spacing. When these 2 signal lines are not very long, what we seen onAB is actually the superposition of 2 pulses.The micro-control made by CMOS technology has high input impedance, high noise and high noise tolerance. The digital circuit is superimposed with 100~200mv noise and does not affect its operation. If the AB line in the figure is an simulation signal, then this interference can not be tolerated. For example, 4L PCB with 1 GND layer or a double-sided board with 1 GND layer, then the interference between the signals becomes small. The reason is that the large-area GND reduces the coated micro-strip impedance of the signal lines, and the reflection of the signal at D is greatly reduced. The constant of the dielectric between the coated micro-strip impedance and the GND is inversely proportional to the square value but it is proportional to the natural logarithm of the dielectric THK. If the AB line is an  simulation signal, interference from the digital circuit signal line CD to AB should be avoided, there should be a large GND area under the AB line, and the distance from the AB line to the CD line should be greater than 2 to 3 times. Partial shielding GND can be used to ground the left and right sides of the wire leads.

⑷ Reduce noise from the power supply

While the power providing energy to the system, it also adds noise to the power supply. The reset lines, ACI and other control lines of the microcontroller in the circuit are easyto interfere by external noise. Strong interference on the electrical network enters the circuit through the power supply, even in battery-powered systems, the battery itself has high frequency noise. Simulation signals in simulation circuits are worse to stand the interference from the power supply.

⑸ Pay attention to the high frequency characteristics of PCB and components

At high frequencies, the distribution of the wire leads, vias, resistance, capacitance and thepress-fit on PCB can not be ignored. The resistance produces a reflection from the high frequency signal, and the capacitance of the wire leads will work. When the length is greater than 1/20 of the wavelength of the noise frequency, an antenna effect will be generated and the noise will be launched outward through the wire lead.

The via holes of the PCB can approximately cause 0.6pf capacitance.

The SMT material in an integrated circuit itself has 2~6pf capacitance.

A connector on a PCB might has 520nH inductance distributed. For 24-pins integrated circuit socket, with 4~18nH inductance distributed.These small distribution parameters in microcontroller systems of low frequency can be 

⑹ Component distribution should be proper

The position of the components on the PCB should be fully considered against the elctro-magnetic interference. One of the principles is that the wire leads between the components should be as short as possible. In the layout, the simulation signal, high-speed digital circuit, source of the noise (such as a relay, large current switch, etc.) should be separated . Reasonably so that the mutual signal coupling can be small.

Handle the GND wire well

Power lines and GND lines are important on PCB. The main means of overcoming electromagnetic interference is the grounding.

For the double-sided board, the layout of GND wires is particularly significant. By usingthe single-point grounding method, the power supply and the GND are connected from the 2 ends of the power supply to the PCB, and the points of the power supply is one by one, so does the GND. On the PCB, there must be multiple returning GND lines, which will be gathered and back to the contact point of the power supply, which is called single point grounding. When connecting to the external signals, normally use shielding cables.For high frequency and digital signals, both ends of the shielding cable are grounding. 

Shielding cable for low-frequency simulation signals, single side of grounding is better.

Circuits that are very sensitive to noise and interference or circuits with particularly high frequency of noise should be shielded with a metal cover.

⑺ Properly use the decoupling capacitance

Good high-frequency decoupling capacitance can remove high frequency components up to 1 GHz. Ceramic capacitance or multilayer ceramic capacitance have better high frequency characteristics. When designing PCB, a decoupling capacitance should be added between the power supply and the GND for each integrated circuit. The decoupling capacitance has2 functions: one is the capacitance storage for the integrated circuit, provides and absorbs the charge/discharge energy of the integrated circuit when the switch opened and closed; on the other hand, the high frequency noise from the devices. The typical decoupling capacitance in digital circuit is 0.1 uf with 5nH inductance distributed. Its frequency of vibration is about 7MHz, which means better decoupling for noise below 10MHz, but hardly works for 40MHz or above.1uf, 10uf capacitance, vibration frequency above 20MHz, it's better for high frequency noise removing. It's advantageous if there is place with 1uf or 10uf de-HF high frequencycapacitance for the power supply to enter the printed board, even if the battery-powered 

systems, this kind of capacitance is still needed.

For every 10 sheets of integrated circuit should add 1 sheet of capacitance, or call it the storage capacitance. The capacitance can be 10uf. The electrolytic capacitance is rolled up by 2 layers of thin film. The rolled structure acts as an inductance at high frequencies,The selection of the decoupling capacitance is not strict, it can be calculated according to C=1/f; that is, take 0.1uf from 10MHz. For the system made of the microcontroller, take 0.1~0.01uf is ok.

3. Some experience in reducing noise and electromagnetic interference.

(1). Use low speed chips as many as possible, high-speed chips can be used in key place.

(2). Crosstalk of resistance can be used to reduce the jump rate at the upper and lower edges of the control circuit.

(3). Try to provide damping for relays in some forms, etc.

(4). Use a low frequency clock that meets the system requirements.

(5). The clock generator should be as close as possible to the device that drives the clock. The shell of oscillator of the quartz crystal should be grounded.

(6). Circle the clock area with a GND wire and keep the clock line as short as possible.

(7). The I/O driver circuit should be as close as possible to the edge of the printed board, make it leave the printed board as soon as possible. For the signals entering the printed board should be filtered, signals from the high noise area should be filtered as well. At the same time, use the crosstalk of the resistance to reduce the signal reflection.

(8). The useless end of the MCD should be connected to high, or GND, or defined as an output end. The end on the integrated circuit should be connected to the GND of the power supply, do not hang it instead.

(9). Do not leave the input terminal of the unused circuit in the air but connect the inputend to the ground.

(10). PCB should use 45-fold lines instead of 90-fold lines to reduce the transmission and coupling of high-frequency signals.

(11). Distinguish the PCB acc.to the frequency and current switch, and distance between the noise component and the non-noise component should be farther away.

(12). Single-sided board and double-sided board can use single-point power supply and single-point grounding, power line and grounding wire are as thick as possible. If the economy is affordable, use multi-layer board to reduce the power supply and grounding inductance.

(13). Keep clock, bus trunk and signals away from I/O lines and press fit connectors.

(14). The analog voltage input line and reference voltage should be as far as possible from the digital circuit signal line, especially the clock.

(15)．For A/D devices, the digital part and the simulation part should be unified rather than crossed.

(16). The clock line is perpendicular to the I/O line and its interference is less than the parallel I/O line, clock component pins are far away from the I/O cable.

(17). The component pins are as short as possible and the pins of decoupling capacitance are as short as possible.

(18). The key lines should be as thick as possible and add protective GND on both sides. The high speed line should be short and straight.

(19). Lines which are sensitive to noise should not be parallel to high current, high speed switching lines.

(20). Do not layout conductor lines underneath the quartz crystal and devices that sensitive to the noise.

(21).For weak signal circuits, closed-loop circuit can not be formed around the low frequency circuit.

(22). Do not form a closed-loop for any signals. If it is unavoidable, make the loop area as small as possible.

(23). One decoupling capacitance per integrated circuit. A small high frequency bypass capacitance should be added to each electrolytic capacitance.

(24).Use a large-capacity tantalum capacitance or a condenser capacitance instead of electrolytic capacitance for the circuit to charge/discharge and store the capacitance. When using a tubular capacitance, the shell should be grounded.